| Both sides previous revisionPrevious revision | |
| learn:programming_c_00prep [2026/08/11 10:48] – azman | learn:programming_c_00prep [2026/08/11 10:51] (current) – azman |
|---|
| The two common things done in a makefile is to define build rules and to define variables. The lines that contains a '=' is usually a variable definition. Any environment variable is imported into ''make'' environment. A rule is defined by specifying a target that is done by specifying a label (or target object name) followed by a ':' character. In the given example, the target is $(PROJECT) - which is a variable and expands to ''single''. Anything that comes after ':' will be considered as a prerequisite. If a target is older than any of its prerequisites, it will be rebuilt by ''make'' tool. The build process is defined by the lines following the target (there can be more than 1 line). Notice that the MUST BE a hard tab character at the beginning of a process line. | The two common things done in a makefile is to define build rules and to define variables. The lines that contains a '=' is usually a variable definition. Any environment variable is imported into ''make'' environment. A rule is defined by specifying a target that is done by specifying a label (or target object name) followed by a ':' character. In the given example, the target is $(PROJECT) - which is a variable and expands to ''single''. Anything that comes after ':' will be considered as a prerequisite. If a target is older than any of its prerequisites, it will be rebuilt by ''make'' tool. The build process is defined by the lines following the target (there can be more than 1 line). Notice that the MUST BE a hard tab character at the beginning of a process line. |
| |
| Imagine now that there are a hundred source files assigned to 'SOURCE'. Using the above rule, changing one source file will cause all the other source files to be recompiled again. This is not very efficient. It is actually useful to know that an executable is built by combining object files and linking them to the respective libraries. Object files (*.o or *.obj) can be built independently. So, to have that, we alter our ''makefile'' to accommodate this. | Imagine now that there are a hundred source files assigned to 'SOURCE'. Using the above rule, changing one source file will cause all the other source files to be recompiled again. This is not very efficient. It is actually useful to know that an executable is built by combining object files and linking them to the respective libraries. Object files (*.o or *.obj) can be built independently. So, to have that, the ''makefile'' needs some additional line(s) to accommodate this. |
| |
| <file make makefile> | <file make makefile> |
| </file> | </file> |
| |
| There are a few new things here. Special variables like $@, $+ and $< are now used. To know what they mean, you may refer to the note at the end of this section. The prerequisites are now object files that needs to be built as well. In order to build these, ''make'' will refer to the second rule ''%.o: %.c'' - which says that any object files (*.o) needs to be built depends on a source C file (*.c) that will be built using gcc with a ''-c'' parameter (compile only). | There are a few new things here. Special variables like $@, $+ and $< are now used. To know what they mean, refer to the note at the end of this section. The prerequisites are now object files that needs to be built as well. In order to build these, ''make'' will refer to the second rule ''%.o: %.c'' - which says that any object files (*.o) needs to be built depends on a source C file (*.c) that will be built using gcc with a ''-c'' parameter (compile only). |
| |
| One thing you should know is ''make'' will use the first matching rule that it finds. So, if you have some object files that depends on both source (*.c) and header (*.h) files, you need to create the rule (''%.o: %.c %.h'') //before// the rule given above. | One important thing to know is ''make'' will use the first matching rule that it finds. So, if you have some object files that depends on both source (*.c) and header (*.h) files, you need to create the rule (''%.o: %.c %.h'') //before// the rule given above. |
| |
| The given information so far about makefiles should be sufficient for basic projects. You will learn, in time, of more advanced ways to specify rules that will show you how the ''make'' tool can be a very powerful build management tool. | The given information so far about makefiles should be sufficient for basic projects. You will learn, in time, of more advanced ways to specify rules that will show you how the ''make'' tool can be a very powerful build management tool. |
